The present disclosure relates generally to semiconductor memory devices, and more particularly, to a bitline precharge circuit and a method for precharging bitlines in a semiconductor memory device.
Recently, there is a need for a semiconductor memory device with high integration and a high operation speed. A low voltage or low power memory device has been developed to secure reliable operation in a low power. In particular, a memory device built in a portable system, e.g., a mobile phone or a notebook computer used outside of an office, has been developed to consume minimum power.
One of the above efforts is to minimize current consumption in a core area of a memory device. The core area, which consists of memory cells, bitlines, and wordlines, is designed according to an extremely minute design rule so that the memory cell has a very small size and operates in a low power.
A bitline precharge operation is important to cell data access speed. The bitline precharge is used to enhance an access time of cell data, xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99, by precharging the bitlines with a predetermined voltage level (currently, xe2x80x9chalf-Vccxe2x80x9d level is commonly used) before accessing the cell data.
FIG. 1 is a block diagram showing a conventional bitline precharge circuit. The bitline precharge circuit includes a driving control unit 100, a precharge circuit driving unit 200 and a bitline precharge unit 300. The driving control unit 100 receives a bitline precharge enable signal as an input, and the precharge circuit driving unit 200 receives a VDD driving signal of a power supply voltage level from the driving control unit 100. The bitline precharge unit 300 precharges bitlines in response to a bitline precharge signal BLEQ provided by the precharge circuit driving unit 200. The bitline precharge unit 300 may be included in a cell array or positioned at an edge of the cell array.
The driving control unit 100 is configured with a converter chain as shown in FIG. 2A, and the precharge circuit driving unit 200 is configured with an inverter structure as shown in FIG. 2B. Referring to FIG. 2C, the bitline precharge unit 300 is configured with a number of transistors to precharge and to equalize a pair of bitlines BITBi and BITTi with a precharge voltage VBLP in response to the bitline precharge signal BLEQ.
Referring back to FIG. 1, the driving control unit 100 outputs the VDD driving signal in response to the bitline precharge enable signal. Then, the VDD driving signal is inputted into the precharge circuit driving unit 200, which in turn, generates the bitline precharge signal BLEQ. The bitline precharge unit 300 precharges the bitlines in response to the bitline precharge signal BLEQ.
When the conventional bitline precharging method is applied to the low power memory device, there is a problem in a parameter tRP related to a bitline precharging time because of a speed delay caused by a relatively high back bias and a low power supply voltage. To solve this problem, a boosted voltage VPP, which has a higher voltage level than that of an external power supply voltage, is used as a driving voltage of the bitline precharge transistors. For example, a VPP driving signal is outputted from the driving control unit 100 as shown in FIG. 1.
FIG. 3 shows simulation results of signals used in the operation of the circuit shown in FIG. 1, which represents driving results when using driving voltages VDD and VPP. When the boosted voltage VPP is employed instead of the power supply voltage VDD, a precharging time of the bitline BL is improved by as much as 13.2 nanoseconds as shown in FIG. 3. However, when the precharging method using the boosted voltage VPP is applied to a field of operational voltage below 2.0 V, there is a problem with the drivability of the boosted voltage VPP being substantially deteriorated. That is, the power supply voltage is boosted by as much as 10% to 50% of the power supply voltage level to make a boosted voltage of about 3.6 V from a power supply voltage of 2.5 V to 3.3 V. Further, to make the boosted voltage of about 3.6 V from a power supply voltage of 1.5 V to 1.8 V, the power supply voltage has to be boosted over 100% of the power supply voltage level. As a result, the drivability of the boosted voltage is considerably deteriorated.
Accordingly, when the bitline precharging transistors (NMOS transistors shown in FIG. 2C) are driven by the boosted voltage, the level of the boosted power voltage VPP is dropped. When the boosted power voltage VPP is dropped, an operational speed precharging the bitlines is delayed and the wordline enabling time driven by the boosted power VPP voltage will also be delayed. Further, as the voltage level of the boosted power voltage VPP is dropped, a refresh problem may occur.
A bitline precharging circuit configured to enhance a precharge operation in a semiconductor memory device without an operational steed delay is described herein. The bitline precharging circuit is configured to minimize power consumption in a bitline precharging operation in the semiconductor memory device. Further, a method for precharging bitlines capable of minimizing power consumption in a bitline precharging operation in the semiconductor memory device is also described herein.
The bitline precharge circuit comprises: a driving control unit configured to output a VDD driving signal and a VPP driving signal in response to a bitline precharge enable signal; a precharge circuit driving unit configured to output a bitline precharge signal of a power supply voltage VDD level or a boosted voltage VPP level in response to the VDD driving signal or the VPP driving signal; and a bitline precharge unit configured to precharge bitlines in response to the bitline precharge signal. A voltage level of the bitline precharge signal reaches the VDD level for a predetermined time from an enabled starting point of the bitline precharge enable signal, and then the voltage level of the bitline precharge signal reaches the VPP level after the predetermined time.
The method for precharging bitlines in a semiconductor memory device comprises: a) inputting a precharge command into the semiconductor memory device; b) enabling a bitline precharge enable signal after the step a); c) enabling a VDD driving signal for a predetermined time from an enabled starting point of the bitline precharge enable signal; d) firstly pulling up a voltage level of the bitline precharge signal to a VDD level in response to the VDD driving signal; e) enabling a VPP driving signal from a moment which the VDD driving signal is disabled; and f) secondly pulling up the voltage level of the bitline precharge signal to a VPP level in response to the VPP driving signal.